Here you can download Paver, a cross-plattform system for exploring low-level software/hardware design.
I've always wanted to try out designing my own microprocessor instruction set, so after a few months of tinkering and senseless drawings I came up with a 16-bit instruction set I thought I liked.
I then wrote a simulator for it in C, then an assembler, then a self-assembling assembler in the target machine code, from which on Paver was self-hosting.
My next goal was to teach myself enough Verilog and Quartus so that I could bootstrap an actual hardware version of my microcontroller on an FPGA chip. I bought a development board and wrote Verilog modules for VGA and PS/2 keyboard, as well as a native SPI driver to interface an SD card.
At this stage, I had a fully standalone development system without external dependencies.
Following on, I updated myself on shader-based OpenGL, and diversified my command line tool into native GUI applications for Android, iOS, macOS and Windows.
Content of the download package
The Windows version is a Win32 application written in C in Visual Studio 2017. The zip file contains the project files.
The macOS version is a Cocoa application written in Objective C. The zip file contains the entire Xcode project.
The iOS version (also C/Objective C) is not maintained at the moment, but the zip file has all the project files for completeness.
The Android version is not maintained at the moment, but the zip file has all the project files for completeness. This version is written in Java using the Java Native Interface.
Finally, the package contains the FPGA design files for the Quartus project (read on if interested in details).
I chose Verilog for its similarity to C, and Altera Quartus II as the IDE because at the time, I was unclear about Xilinx' product offering and licencing. MY design is currently not pipelined, and runs fine on a Terasic DE1-SOC board with 1152x864 VGA graphics and PS/2 keyboard at 83 MHz, with most instructions using 2 clock cycles. I did implement interrupt instructions which I'm using to detect various system events like keypresses, timers etc, but I don't think the model is scalable or clean enough. I will try and get to a pipelined design with proper interrupts time permitting.
The only addition I made to the development board is to connect an SD card module to it in SPI mode, but an SD card is not essential as the FPGA contains an initial RAM image. In short, you should be able to just flash the board with the .jic file provided in the download package and watch Paver come up without wiring up an SD card breakout. For this to work, set SWITCH0 of the board to ON before applying power. This will bypass the SD card boot sequence.
Finally, should you be curious about writing software for Paver yourself, take a look at its BIOS, assembler, text editor and command line interpreter, written in around 10k lines of 8T3 assembler.
Status of this project (October 2021) I am currently not working on Paver, but put in quite a bit of work about 2 years or so ago, cleaning up the firmware, factoring the assembler and adding a filesystem. These changes haven't been reflected in the Verilog source yet (there were a few changes made to the VM, namely removing the interrupt system).
As my other hardware project (McBastard) stabilizes and will be finished, I am planning to revisit Paver and provide a more polished version. This will most likely be happening when I code a Verilog version of McBastard. As I quite liked working with my Paver core on the DE1-SOC board, I might use Paver and its VGA and PS/2 modules to bootstrap a McBastard core.